1. Field of the Invention
The present invention relates to an output circuit for data transfer, which is capable of outputting binary logic signals having different logical amplitudes and applied to a semiconductor device.
2. Description of the Related Art
The current trend towards automotive electronics has brought about an increase in the number of electronic devices including the system controller and, hence, an increase in the number of electric wires to be laid between these electronic devices. To decrease the number of electric wires, the data between the electronic device are transmitted in a serial manner through a dual wires as disclosed in U.S. Pat. Nos. 4,715,031, 4,929,941 and 5,001,642.
Standardization of serial data transmission systems for use in automobiles has been worked out by the SAE (Society of Automotive Engineers of America) which classifies the serial data transmission system into three classes A to C according to the transmission speed required. Class A is for low-speed transmission under 125 Kbps and is applied to the device control systems in the body including lamps, power windows, and door locks. Class B is for medium-speed transmission and is applied to status information systems such as electronic meters, navigators and vehicle diagnosis apparatus. Class C is for high-speed transmission over 125 Kbps, and is applied to real-time control systems such as the engine control system, the brake control system and the transmission control system.
SAE also determines a standard J1850 as an Automotive LAN communication protocol covering the classes A to C. The physical layer of J1850 includes two types: one is a low-speed type while the other is a medium-speed type. The medium-speed type has a transmission rate of 41.6 Kbps, PWM (Pulse Width Modulation) form, dual-wire voltage drive method and use of wake-up signals, and has a connection form as shown in FIG. 6.
A couple of signal transmission wires BP and BM are used to connect n pieces of electronic devices T1 to Tn including system controller. The signal transmission wire BM is connected at one end through a resistor R1 to a power supply wire VCC and at the other end through a resistor R3, which value is equal to the value of the resistor R1, to the power supply wire VCC, while the signal transmission wire BP is connected at one end through a resistor R2 to a grounding wire GND and at the other end through a resistor R4, which value is equal to the value of the resistor R2, to the grounding wire GND. According to the dual-wire voltage drive method, the potentials V(BP) and V(BM) at the signal transmission wires BP and BM, respectively, vary in a manner shown in FIG. 9A for example. Normal signal voltage V(BP)-V(BM) has logical amplitude which is 200 mV or over at a dominant state, while wake-up signal voltage V(BP)-V(BM) has logical amplitude which is 2.5 V or over at a dominant state. The logical value "1" and "0" of ordinary signals are determined by pulse widths of the dominant state as shown in FIGS. 9B.
In order that two kinds of binary logic signals having different logical amplitudes are transmitted, a semiconductor device 10 is required to have a driver circuit 12 for ordinary signals and a driver circuit 13 for wake-up signals both of which are connected to a control circuit 11, as well as a receiver 14 for ordinary signals and a receiver 15 for wake-up signals both of which also are connected to the control circuit 11. The control circuit 11 performs local control of input/output devices 17 to 19 and receives status signals and other signals from these input/output devices, through an I/O interface 16.
FIG. 7 illustrates the construction of the output stage of the control circuit 11 having AND gates 111, 112 and inverters 113 to 115 and the constructions of the ordinary driver circuit 12 having pMOS transistors 121, 122 and nMOS transistors 123, 124 and the wake-up driver circuit 13 having a pMOS transistor 131 and an nMOS transistor 132.
When the mode signal is a high level so as to transmit an ordinary signal, the AND gate 112 is closed so that both the pMOS transistor 131 and the nMOS transistor 132 are kept in an off state. In this state, when the input signal SI shifts to high level, the pMOS transistor 121 turns on and the potential of the signal transmission wire BP raises from the ground level, while the nMOS transistor 123 turns on and the potential of the signal transmission wire BM falls down from the power supply voltage VCC. Conversely, when the input signal SI is shifted to low level, the pMOS transistor 121 turns off and the potential of the signal transmission wire BP falls down to the ground level, while the nMOS transistor 123 turns off and the potential of the signal transmission wire BM raises up to the power supply voltage VCC.
When the mode signal is of low level so as to transmit a wake up signal, the AND gate 111 is closed so that both the pMOS transistor 121 and the nMOS transistor 123 are kept in off state. In this state, when the the input signal SI is shifted to high level, the pMOS transistor 131 turns on and the potential of the signal transmission wire BP raises from the ground level, while the nMOS transistor 132 turns on and the the potential of the signal transmission wire BM falls from the power supply voltage VCC. Conversely, when the input signal SI is shifted to low level, the pMOS transistor 131 turns off and the potential of the signal transmission wire BP falls to the ground level, while the nMOS transistor 132 turns off and the the potential of the signal transmission wire BM raises to the power supply voltage VCC.
FIG. 8 illustrates the construction of the receiver 14 for ordinary signals. The receiver 14 has a voltage follower 141, the output node of which is connected through a resistor 142 to non-inversion input node of the operation amplifier 143, and a resistor 144 connected between the non-inversion input node of the operation amplifier 143 and the output node of the same. The operation amplifier 143, resistor 141 and resistor 144 compose a comparator having hysteresis. The output of the operation amplifier 143 becomes a high level only when the potential of the signal transmission wire BP is higher than that of the signal transmission wire BM by an amount which is determined by the resistors 142 and 144.
The wake-up receiver 15 has a construction which is the same as that shown in FIG. 8, except for the resistance values of the resistors 142, 144. This receiver 15 responds only to a wake-up signal and does not respond to ordinary signals. The wake-up signal puts into operation an electronic device, e.g., a back sonar whose operation has been slept.
It has thus been necessary to employ two different types of driver circuits, i.e., the driver circuit 12 for ordinary signals and the driver circuit 13 for wake-up signals. The area occupied by each of the pMOS transistors 121, 122, nMOS transistors 123, 124, pMOS transistor 131 and nMOS transistor 132 on chip has to be about 100 times larger than that of a MOS transistor in the control circuit 11, in order to obtain a sufficiently large driving power electric current of which is dozens of mA. Consequently, the chip size of the semiconductor device 10 becomes large.